Phase Locked Loops (PLL) are widely used in many different applications and domains of the electrical engineering, such as in telecommunications where they are mainly used to synthesize a clock signal or a carrier signal which allows various devices to transpose base band signals to targeted modulation channels. In such applications, for instance, the output signal can be in the High Frequency (HF) or (Radio Frequency) RF domains.
As generally described by the basic PLL chronogram illustrated in FIGS. 1(a)-1(c), a PLL circuit generates an output signal whose phase is related to the phase of a reference signal 100. This output signal is generated by a Voltage Controlled Oscillator (VCO) whose voltage is controlled by the feedback loop. As shown in the top of FIG. 1(a), the VCO phase output signal 102 is divided in order to be compared with the reference phase by a phase frequency differentiator (PFD). A divider generates a divided signal 104 whose frequency value is close to the reference signal 100's frequency value. The PFD generates a signal 106 whose pulse width corresponds to the phase displacement of the reference signal 100 and divided signal 104. The charge pump (CP) sources or sinks a current to the loop filter during the PFD pulse width as indicated by PFD UP signal 106 and PFD DN 108, respectively, and as shown in FIG. 1(b) and described in more detail below.
Loop stabilization and noise filtering are some of the objectives of the loop filter which is adapted to generate the VCO control voltage. Depending on, for example, the applications or the telecommunication standards concerned, the requirements for the PLL may vary, but they usually relate primarily to the same issues. One important PLL design configuration concerns the current consumption of the PLL, which should be as low as possible, especially for mobile devices supplied by batteries. Another design configuration is noise. For example, mobile phone standards like Global Standard for Mobile (GSM) require specific noise values at 400 kHz, which makes it necessary to have a short bandwidth (about 100 kHz for GSM) and thus involves the use of big capacitance values for the loop filter.
Loop filter capacitance can be reduced by the use of a dual path loop filter. As will be further described below, the expected loop filter transfer function can be achieved with a lower silicon area when using two charge pumps, as opposed to a single charge pump in the PLL. Accordingly, existing solutions can be classified into two classes: those with a single path loop filter and those with a dual path loop filter. An example of a PLL architecture based on a single path (single charge pump) loop filter is shown in FIG. 2(a). Therein, and as described above with respect to FIG. 1, a PFD 200 receives both a reference signal 202 and a version of the VCO 204's output signal divided by divider 206 (feedback signal 207). The PFD 200 outputs up/down signals whose pulse width corresponds to the phase displacement of the output signal. The CP 208 sources or sinks a current to the loop filter 210 during the PFD pulse width, and the loop filter 210 outputs the control signal to VCO 204 which, in turn, generates the oscillator signal as shown in FIG. 2(a).
The single path loop filter (SPLF) can be illustrated as shown in the circuit diagram representation of FIG. 2(b). Therein, the single charge pump 220 sources current I to loop filter 230 when the Up switch is closed and the Dn switch is opened and sinks current to the loop filter 230 when the Up switch is opened and the Dn switch is closed. In the single path loop filter architecture of FIGS. 2(a) and 2(b), design attention is paid to improve noise, power consumption and linearity. Linearity defaults mainly occur when the phase of the output of the PLL and the reference phase are synchronized such that the PFD-charge pump combination works alternatively on phase-lead and phase-delay. At steady state, since the PLL locks the VCO output phase on the reference phase, the VCO divided signal edge comes close to the reference edge such that the single charge pump 220 injects no charges to the loop filter 230.
This PLL feedback action is obtained by the UP and DN control signals, e.g., such as those shown in FIG. 1(a) which are generated by the PFD 200 as described above. As seen in FIG. 1(a), the UP signal 106 is a pulse width modulated signal from one edge of the reference signal 100 to the next edge of the VCO divided signal 104. Conversely, the DN signal 108 is a pulse width modulated signal from one edge of the VCO divided signal 104 to the next edge of the reference signal 100 when it comes later.
The charge pump current I in FIG. 2(b) and Iup/Idn in FIG. 1(b) are subject to potential mismatches. Any Iup/Idn mismatch between currents Iup and Idn of the current sources switched by control signals UP and DN, respectively, creates a non-linearity in the charge pump gain characteristic (as shown in FIG. 1(c)) which, in turn, creates undesirable parasitic spurs in the PLL output frequency spectrum. One way to make a more linear single charge pump may be to add a continuous current source at its output, in order to move the steady state into a linear region as shown in FIG. 1(d). However there are some drawbacks to this SPLF solution including: that the loop filter can have a large area due to the short bandwidth; that current leakage by the capacitors related to their size (the thinner the oxide is, the more the capacitor leaks, in particular in newer capacitor technologies), and, significantly, additional noise due to the small but continuous current source used to linearize the charge pump.
More specifically, and looking again at FIG. 2(b), the charge pump 220's current I is sourced in the RC loop filter 230, including an integrator capacitor Ca for noise filtering efficiency, and resistor Rb and capacitor Cb which ensure the loop stability by adding a zero in the PLL transfer function. The capacitors Ca and Cb can be large to optimize PLL noise filtering, implying the need for a large silicon area for these capacitors and correspondingly increasing current leakage through polysilicon capacitor grids.
Alternatively, the same charge pump-loop filter transfer function can be achieved using a smaller capacitance-silicon area if a dual path loop filter architecture is used. An example of this other class of PLL architecture, i.e., the dual path loop filter, which has been developed for loop filter area reduction based on the use of two charge pumps, is shown FIG. 3(a). Therein, elements having similar reference numerals, albeit with a preceding “3” instead of “2”, as in FIG. 2(a) operate in a similar manner. It can be seen that the only difference between the PLL of FIG. 2(a) and that of FIG. 3(a) is the provision of two charge pumps 308a and 308b in FIG. 3(a) versus a single charge pump in FIG. 2(a).
A circuit element diagram of an exemplary dual path loop filter (DPLF) is shown in FIG. 3(b). Therein, charge pump current is sourced in an RC loop Filter 310 which includes an integrator capacitor C1 (corresponding to Ca in the example of FIG. 2(b)) for noise filtering efficiency, and resistor R2 (corresponding to Rb in FIG. 2(b)) and capacitor transfer function. In this DPLF architecture, a second charge pump 312 is provided having a nominal current β*I which is different from the nominal current α*I of the first charge pump 314. Moreover, to work properly, when one charge pump sources a current, the second charge pump has to sink its counterpart current. A system study has shown that the transfer function associated with an SPLF architecture can be preserved in a DPLF architecture if the capacitance ratio Ctot—dplf in the DPLF system is maintained as:Ctot—dplf=(α−β)*Ctot—splf  (1)where:
Ctot_dplf represents the total capacitance of dual path loop filter;
Ctot_splf corresponds to the equivalent single path loop filter; and,
α and β correspond to the charge pump current ratio relative to a nominal current I.
However, the provision of the second charge pump in a DPLF architecture increases the power consumption of the circuit, increases the noise and also leads to the possibility that charge pump source mismatches can occur. Mismatches can occur both because two charge pumps are used and because the PFD signals UP and DN described above are inverted.
Accordingly, it would be desirable to provide methods, devices and systems which address these, and other, challenges.